1. Field of the Invention
The present invention relates to integrated semiconductor devices. More particularly, the present invention relates to an integrated semiconductor device that can switch between an FP (Fast Page) mode and an EDO (Extended Data Output) mode by the so-called bonding option determined by the bonding connection of a pad in a dynamic random access memory (referred to as DRAM hereinafter).
2. Description of the Background Art
FIG. 3 is a block diagram showing an entire structure of a conventional DRAM. Referring to FIG. 3, an externally applied row address strobe signal RAS is provided to a RAS buffer 1. RAS buffer 1 generates an internal RAS signal which is provided to an address control circuit 4. In response, address control circuit 4 provides an externally applied row address signal to an address buffer 7. Address buffer 7 provides an X address signal to a row decoder 11, whereby the X address of a memory cell 8 is specified.
Following an entry of row address strobe signal RAS, a column address strobe signal CAS is applied to a CAS buffer 2 to be converted into an internal CAS signal. The internal CAS signal is applied to address control circuit 4, a write control circuit 5, and a readout control circuit 6. Address control circuit 4 responds to the internal CAS signal to provide an externally applied column address signal to address buffer 7. In response to a column address signal, address buffer 7 provides an Y address signal to a column decoder 9, whereby the Y address of memory cell 8 is specified. A write enable signal WE for identifying read/write is provided to a WE buffer 3, whereby an internal WE signal is generated. Write control circuit 5 is enabled in response to an L level (logical low) of signal WE, whereby the data in an input buffer 14 is written into memory cell 8 via a write driver 15. In a readout operation, write enable signal WE attains an H level (logical high), whereby readout control circuit 6 activates a pre-amplifier 12 and an output buffer 13. The data in memory cell 8 is read out by a sense amplifier 10 to be output via pre-amplifier 12 and output buffer 13.
In the past several years, the demand for increase in the operation speed in such DRAMs shown in FIG. 3 is appreciated, leading to the development of various operation modes. One such operation mode is the EDO mode. The EDO mode is a faster version of the FP mode. According to a specification in which the time from a rise of a row address strobe signal RAS to a data output is tRAC=60 nsec., the cycle time for an EDO mode is 25 nsec., which is drastically higher than the cycle time of 47 nsec. for an FP mode. In order to switch between such modes differing in the required rate by means of the so-called bonding option determined by the manner of connection between the bond and pad in one chip, the operation in an internal circuit must be varied between an EDO mode and an FP mode. More particularly, the specification of the shortest term of an L level of column address strobe signal CAS (tCAS) is 15 nsec. in an FP mode in contrast to 10 nsec. in an EDO mode. This is extremely short with respect to a writing operation which is executed only during a period where column address strobe signal CAS attains an L level. This will be described in more detail hereinafter.
FIG. 4 is an electrical circuit diagram showing partially the data writing system of a write control circuit, an input buffer, a write driver, and a memory cell of the DRAM of FIG. 3. Referring to FIG. 4,.internal row address control signal ZRASF is inverted by an inverter 21 to be applied to one input terminal of an NAND gate 41. An internal column address strobe signal ZCASF is inverted by an inverter 22 to be applied to one input terminal of an NAND gate 42. NAND gates 41 and 42 form an RS flip-flop. An internal write enable signal ZWEF is inverted by an inverter 23 to be applied to one input terminal of an NAND gate 43. The output of inverter 22 and the output of NAND gate 42 are applied to the other input terminals of NAND gate 43. The output of NAND 43 is inverted by an inverter 24 to be provided to an inverter 25 as a CASNW signal. This CASNW signal is further inverted by inverter 25 to be applied to one input terminal of an NOR gate 44. External data EXTDIN is applied to the other input terminal of NOR gate 44. The output of NOR gate 44 is inverted by an inverter 26 to be applied to a transmission gate 50 forming input buffer 14 shown in FIG. 3. In response to an internal latch signal ZDIL, the output of inverter 26 is latched by a latch circuit formed of an inverter 27 and a clocked inverter 51. The latched output is provided as an internal input data signal WDG via inverters 28, 29 and 30 to be applied to a write buffer 60. Write buffer 60 is included in memory cell 8.
Internal input data signal WDG is applied to one input terminal of an NOR gate 46 in write buffer 60 and to an inverter 33. Internal input data signal WDG is inverted by inverter 33 to be applied to one input terminal of an NOR gate 45. A write buffer enable signal WBE is inverted by an inverter 32 to be applied to respective other input terminals of NOR gates 45 and 46. The outputs of NOR gates 45 and 46 are applied to I/O lines IO and ZIO via a write buffer formed of n channel MOS transistors 52-55. I/O line IO is connected to a bit line BL via a transfer gate 56. I/O line ZIO is connected to a bit line ZBL via a transfer gate 57. A chip select signal CSL is applied to the gates of transfer gates 56 and 57.
FIG. 5 is a timing chart for describing the operation of the write circuit of FIG. 4, particularly showing a sufficiently long and short tCAS (the term of the column address strobe signal attaining an L level) of an Early Write cycle (the state of write enable signal WE attaining an L level when column address strobe signal CAS is low) in an FP mode.
A writing operation is initiated by column address strobe signal CAS and write enable signal WE both attaining the L level. Following the fall of internal row address strobe signal ZRASF to an L level as shown in FIG. 5(a), the transition of internal column address strobe signal ZCASF and internal write enable signal ZWEF to an L level as shown in FIG. 5 (b) and (c) causes the output of NAND gate 43 to be pulled down to an L level and then inverted by inverter 24. Signal CASNW attains an H level as shown in FIG. 5 (e), and NOR gate 44 is activated to which external data input EXTDIN is applied. Here, signal WDG attains an H level as shown in FIG. 5 (g) since internal data load signal ZDIL attains an H level as shown in FIG. 5 (f). In response to CASNW attaining an H level, external data input EXTDIN shown in FIG. 5 (d) is transmitted as signal WDG.
Shortly after the data has been entered, internal column address strobe ZCASF and internal write strobe signal ZWEF attaining an L level causes internal data load signal ZDIL shown in FIG. 5 (f) to be pulled down to an L level, whereby the data is latched in input buffer 50. Signal WBE that activates write buffer 60 is also generated from internal column address strobe signal ZCASF and internal write enable signal ZWEF attaining an L level. Signal WBE is pulled up to an H level as shown in FIG. 5 (h) after the transmission of signal WDG, whereby write buffer 60 is activated. Data corresponding to an H level or L level of signal WDG shown in FIG. 5 (g) is written into bit line BL selected by chip select signal CSL.
Signal WBE is a pulse signal taking a constant width when driven to an H level by a self timer. This pulse width must be great enough to reverse the H level and the L level of bit lines BL and ZBL determined by the latch of a sense amplifier (not shown) via an I/O line. However, internal column address strobe signal ZCASF is immediately pulled up to an H level in response to signal WBE driven to an H level during the short term of the tCAS shown in FIG. 5 since the WBE pulse is forcefully disabled by internal column address strobe signal ZCASF. Therefore, write buffer 60 is rendered inactive prior to the inversion of bit lines BL and ZBL, so that data cannot be written.
Although the above-described problem is not encountered in an FP mode in a conventional DRAM since the specification of the tCAS was sufficiently great, this problem is noticeable in the new EDO mode since the specification of the tCAS is extremely reduced therein. A sufficient activation time period of the write buffer cannot be obtained since internal column address strobe signal ZCASF is pulled up to an H level too early.